There are a number of conventional processes for packaging integrated circuits. In many situations it is desirable to form solder bumps directly on an integrated circuit die. Typically, the solder bumps are formed on the active surface of the wafer before the individual dice are cut (singulated) from the wafer. When the resulting die is mounted on a substrate or other appropriate carrier, the solder bumps may be reflowed to create electrical connections to the die. This style of electrically connecting integrated circuits is often called “flip chip” mounting, because the die frequently must be “flipped” to place its active surface containing solder bumps into contact with the substrate to which the chip is to be attached. As integrated circuit devices and packaging get smaller and smaller, there are more situations where a flip chip type mounting is desirable.
One type of packaged integrated circuit device is commonly referred to as a “power package.” Generally power packages include semiconductor devices having pins or lines that carry much higher currents (and sometimes higher voltages) than typical semiconductor devices. At the same time, many power devices also have signal lines that must be able to accommodate relatively high speeds. Due to a number of constraints, flip chip packaging techniques have not been widely used in power packages. Accordingly, although existing surface mount techniques work well, there are continuing efforts to develop even more efficient designs and methods for surface mounting the integrated circuit components in order to accommodate many different application requirements including the unique challenges of power packages.